In the semiconductor fabrication art, there is an increasing necessity for devices which have very low leakage currents in both logic and in memory circuits. The increased density of both logic and memory chips has produced the consequent need to maintain these chips at a level of power dissipation which can be cooled economically. This requires the circuits used to have a low power dissipation. Such lower power circuits are generally achieved by designing circuits to operate at currents lower than previous generation circuits. This low operating current requirement, however, makes it necessary to measure more accurately the distribution of discrete device leakage currents both in the forward and in the reverse mode of operation as the leakage current can be large enough to adversely affect circuit operation.
In the field of semiconductor device design and manufacture, such devices must be tested to determine whether their electrical parameters meet design specifications or to determine whether the device has defects. Semiconductor circuits are designed assuming that the electrical characteristics of the component devices will fall within certain specified ranges. When a device characteristic deviates from this assumed specification, however, the circuit will fail. With the increased density of both semiconductor logic and memory chips, the need to maintain chip power dissipation within a range which can be economically cooled requires circuits that are designed to operate at very low power dissipation levels. For example, for a high density semiconductor memory chip to maintain low chip power dissipation, it is desirable that all memory cells on the chip which are in standby condition, that is in the condition when data is neither being written into nor read therefrom, should consume the minimum power which the semiconductor design will allow. To achieve this, the memory cells are designed so that the standby currents are the minimum necessary to retain data stored therein. This results in a cell being sensitive to low level currents at cell nodes to which devices at low forward bias and reverse bias are connected. If these low level currents exceed the limits assumed in the design, the cell will fail. Such failures can substantially reduce the number of functional chips yielded by the manufacturing process.
A VLSI semiconductor chip contains hundreds of thousands of devices. When such a chip must operate at low power, it is essential that the discrete device leakage current distribution be accurately known. This is necessary so that the circuits can be designed to tolerate the worst case leakage which can occur.
One type of device for which leakage current is desired to be measured is the Schottky barrier diode (SBD) which is commonly used in both logic and memory circuits. A Schottky barrier diode is typically formed by depositing a metal over an etched opening in the top insulating layer of the semiconductor wafer. Although the mean leakage current of such a device is in the sub-pico ampere range, the upper bound of the leakage current distribution can be considerably higher, e.g., in the nanoampere range. To obtain an accurate determination of the upper bound of the leakage current for Schottky barrier diodes on a chip, a large number of discrete devices must be measured. This measurement must be periodically done during high volume manufacture of the chip so that if the upper bound increases, corrective action can be taken to reduce leakage and maintain the desired level of manufacturing yield.
High volume manufactured semiconductor chips are typically tested by automatic electrical testers which step probes from chip site to chip site over the semiconductor wafer. The measured data is automatically sent to and stored in a host computer. Such testers can measure currents accurately in the micro ampere range and possibly down to 100 nanoampere but not in the sub-nanoampere range. Therefore, such currently available testers cannot be used to measure the upper bound of a leakage current distribution in a discrete device such as a Schottky barrier diode. Using other measurement techniques to measure this distribution upper bound of leakage current for a Schottky barrier diode, however, is not sufficiently fast so as to be suitable for use in a high volume manufacturing environment. Accordingly, the prior art testers and methods do not provide any means for measuring leakage current in the sub-nanoampere range in a high volume manufacturing environment for semiconductor devices.
Various devices are known in the prior art for measuring low currents. For example, a circuit for doing so is described and claimed in the patent of McPhail, U.S. Pat. No. 3,702,967 entitled "Electronic Test System Operable in Two Modes". This patent describes a circuit making a parametric test system that can provide a forcing current at a predetermined level in one mode with a voltage being measured or a forcing voltage of a constant potential in another mode with a current being measured. The circuit does not provide any means to extend the range of conventional automatic testers to measure leakage currents in the sub-nanoampere range.
Another circuit for measuring P-N junction device leakage is described and claimed in the patent of Verkuil, U.S. Pat. No. Re. 29,918 entitled "Contactless LSI Junction Leakage Testing Method", reissued on Feb. 20, 1979. This patent describes a circuit for contactless measuring P-N junction leakage currents by inductively coupling high frequency oscillations to a semiconductor specimen which is simultaneously subjected to a pulsed light of selected intensity. The described circuit does not measure discrete device leakage current in response to a fixed applied DC voltage nor does it measure currents in the sub-nanoampere range.
Typical low current measuring devices used in the laboratory may be used to measure currents in the picoampere range. These measuring devices when used to measure low currents in a circuit on a chip are quite difficult to use because the probe capacitance and the like cause the device to respond very slowly. Hence, this approach is not suitable for use in a manufacturing testing environment where such current measurements have to be made quickly and accurately.